This invention relates to a semiconductor integrated circuit device and to a technique which will be effective when applied, for example, to a full custom semiconductor integrated circuit device consisting of RAMS (Random Access Memories) and a logic circuit for controlling them.
A conventional semiconductor integrated circuit device with built-in RAMS in a gate array is disclosed, for example, in "Nikkei Electronics", June 3, 1985, No. 370, pp. 151 - 177, published by Nikkei McGrawHill Co., and "Electronic Technique", November, 1985, pp. 32-39.
In the semiconductor integrated device of the kind described above which incorporates RAMS in the gate array, a logic unit consisting of the gate arrays is disposed at the center of chip and RAMS are disposed around the logic unit to secure versatility of the gate arrays.
High speed accessibility of ultra-high speed memories (e.g. buffer storages, control storages, etc.) used as the peripheral devices of a central processing unit (CPU) in a general purpose large scale computer or of vector registers in a super computer has great significance for improving system performance. A conventional ultra-high speed memory includes RAM of a multi-bit structure requiring a high speed operation and a logic circuit for controlling RAM and they are composed of separate semiconductor integrated circuit devices, respectively. Therefore, there is an inevitable limit as to how much the operation speed can improved by thus reducing the signal propagation delay time in wirings connecting these semiconductor integrated circuit devices and by reducing the circuit delay in input/output buffers. Accordingly, attempts have been made to utilize the semiconductor integrated circuit device consisting of the logic circuit consisting of the gate array and RAM having the multi-bit structure, as described above.
Input signals such as address signals, write data and so forth that are inputted to a RAM of the multi-bit structure are received by an input latch circuit in accordance with a predetermined clock signal. This reduces skews between the input signals and the RAM can thereby operate at a high speed in synchronism with a system clock.
The input latch circuit described above consists of standard flip-flop circuits FF5-FF7 which in turn consist of gate arrays as typified by a data input latch circuit DL shown in FIG. 15 of the accompanying drawings. In the same way as in other standard logic circuits, these flip-flop circuits employ ECL series gates as the fundamental structure and are equipped with NOR gate circuits for receiving an inversion internal enable signal en0 and an inversion timing signal .phi.0, example, at their clock input terminals, respectively. When both of the inversion internal enable signal en0 supplied from an enable shaping circuit ENT0, not shown, through clock amplifiers CA1, CA2 and CA3 and the inversion timing signal .phi.0 supplied from a clock shaping circuit CPT0, not shown, through clock amplifiers CA4, CA5 and CA6 are at the low level, the data input latch circuit consisting of these flip-flop circuits FF5-FF7 receives the input data IND0-INDm and transmits them as complementary write data wrd0, wrd0-wrdm to RAM.